1. Field of the Invention
The present invention relates to a reference voltage generator, and more particularly to a reference voltage generator generating a reference voltage using a clamp voltage generated with a voltage clamp circuit as a power supply.
2. Description of Related Art
Along with a recent tendency toward reduction in power supply voltage and power consumption of a semiconductor integrated circuit, an influence of a power supply voltage change or temperature change on circuit operations of the semiconductor integrated circuit becomes large. Thus, a high stability against such change has been required of the circuit. As an example of the semiconductor integrated circuit, there is a reference voltage generator. The reference voltage generator generates a reference voltage used for driving the other circuits, and needs to have a higher stability than that of the other circuits.
An example of the reference voltage generator is disclosed in Japanese Unexamined Patent Publication No. 63-266509 (Related Art 1). FIG. 6 shows a reference voltage generator 100 of the Related Art 1. The reference voltage generator 100 of the Related Art 1 generates, at base terminals of reference voltage determining transistors Q103 and Q104, a reference voltage VBG that is derived from Expression 1 based on reference voltage determining transistors Q103 and Q104, and resistors R1 and R2. In Expression 1, a base-emitter voltage of each transistor is represented by Vbe [transistor number].VBG=R1×2((Vbe[Q103]−Vbe[Q104])/R2)+Vbe[Q103]  (1)
The reference voltage becomes an output voltage Vo as a result of enhancing a current power with an output buffer transistor Q105. The output buffer transistor Q105 is diode-connected, and its base terminal is connected with base terminals of the reference voltage determining transistors Q103 and Q104. Further, the reference voltage generator 100 of the Related Art 1 is configured such that level-shift transistors Q107 and Q108 make the collector voltage of the reference voltage determining transistor Q103 equal to the output voltage Vo. Here, provided that a base-emitter voltage of each transistor is represented by Vbe[transistor number], a collector voltage Vc[Q103] of the reference voltage determining transistor Q103 is expressed by Expression 2. Incidentally, base-emitter voltages of the level-shift transistors Q107 and Q108 are at substantially the same level.Vc[Q103]=Vo−Vbe[Q107]+Vbe[Q108]≅Vo  (2)
Through the above operations, the reference voltage generator 100 of the Related Art 1 makes a collector voltage of the reference voltage determining transistor Q103 substantially equal to a collector voltage of the output buffer transistor Q105 to thereby suppress the Early effect of the transistors regardless of the output voltage Vo and suppress variations in output voltage Vo.
However, the collector voltage Vc[Q104] of the reference voltage determining transistor Q104 of the Related Art 1 is derived from Expression 3 based on a power supply voltage VCC and a base-emitter voltage Vbe[Q102] of the transistor Q102.Vc[Q104]=VCC−Vbe[Q102]  (3)
As apparent from Expressions 2 and 3, if the power supply voltage VCC is changed, a rate of change of Vc[Q104] is different from that of Vc[Q103].
Further, a base-emitter voltage Vbe of the transistor is generally expressed by Expression 4.Vbe=(kT/q)ln(1+Vce/Va)Ic/Is  (b 4)where k represents Boltzmann constant, T represents an absolute temperature, q represents a charge quantity, Vce represents a collector-emitter voltage of a transistor, Va represents the Early voltage of a transistor, Ic represents a collector current of a transistor, and Is represents a reverse saturation current of a transistor.
As understood from the above description, in the reference voltage generator 100 of the Related Art 1, if the power supply voltage VCC is changed, Vc[Q103] and Vc[Q104] are changed at different rates, so Vce derived from Expression 4 differs between the reference voltage determining transistors Q103 and Q104. A change rate of Vbe differs between the reference voltage determining transistors Q103 and Q104, so VBG derived from Expression 1 is changed.
In order to solve the above problems, Japanese Unexamined Patent Publication No. 2003-7837 (Related Art 2) discloses a technique of stabilizing a power supply voltage of the reference voltage generator. FIG. 7 shows a reference voltage generator 200 of the Related Art 2. As shown in FIG. 7, the reference voltage generator 200 of the Related Art 2 generates a voltage VCC2 that less varies, based on a power supply voltage VCC1 that largely varies. A band-gap circuit 201 generates a reference voltage Vref with the voltage VCC2 used as a power supply.
That is, the reference voltage generator 200 of the Related Art 2 generates the voltage VCC2 that less varies and then generates a reference voltage Vref with the voltage VCC2 used as a power supply to suppress variations in reference voltage Vref relative to the power supply voltage change.
The reference voltage generator of the Related Art 1 has a problem in that the output voltage change relative to the power supply voltage change increases. In the Related Art 2, the regulator 202 is provided to suppress variations in power supply voltage for the band-gap circuit 201, and the regulator 202 has an operational amplifier. Thus, the Related Art 2 has a problem in terms of a performance for realizing a low-voltage operation or low power consumption. For example, the power supply voltage VCC2 necessary for the band-gap circuit 201 to output a desired reference voltage Vref is about Vref+1.5 V, and the power supply voltage VCC1 of the regulator 202 necessary for generating the power supply voltage VCC2 is about VCC2+1.5 V. Therefore, the reference voltage generator 200 of the Related Art 2 should set the power supply voltage of about Vref+3.0 V for obtaining the reference voltage Vref, so a low-voltage operation is difficult.